NoBug Tunisia is seeking

verification engineers

to work on different projects, and help drive pre-silicon functional verification.

Role:

Develop C++ reference models of hardware blocks for functional verification of RTL.
Develop test benches, reusable verification components (e.g. BFMs, scoreboards) for functional verification.
Create functional verification plans.
Develop and debug constrained-random and directed test cases towards coverage driven verification closure.

Essential technical skills required:

•2+ years in RTL design and verification, with an emphasis on verification.
•worked in block-level and/or system-level verification.
•worked C++ and/or System C modeling.
•Strong Unix and scripting knowledge – Perl, Python, TCL, bash, c-shell
•Strong knowledge of System Verilog
•Familiarity with uVM, eRM, VMM methodologies (from higher to lower interest)
•Knowledge of Hardware/software co-simulation
•Preparing detailed verification plans
•Developing, testing, and integrating C++/System C models
•Developing verification components
•Executing metric-driven functional verification using random stimulus coupled with cover groups and System Verilog Assertions.
•The successful candidate needs to be highly pro-active, and be willing to help address whatever design and verification issues arise.

In order to apply please send your application to :